System and method for superconducting multi-chip module

ABSTRACT

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation of U.S. patent applicationSer. No. 16/599,985, filed Oct. 11, 2019, now U.S. Pat. No. 11,121,302,issued Sep. 14, 2021, which is a non-provisional of, and claims benefitof priority under 35 U.S.C. § 119(e) of, U.S. Provisional PatentApplication No. 62/744,494, filed Oct. 11, 2018, the entirety of whichare expressly incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to the field of manufacturing ofsuperconducting integrated circuit modules, and packages bonding aplurality of such circuits.

BACKGROUND OF THE INVENTION

All references cited herein are expressly incorporated herein byreference, for all purposes.

The technology of superconducting integrated circuits has beendeveloping in recent years, although the integration scale remainssomewhat below that of mainstream semiconductor technology. The mostadvanced superconducting integrated circuits are based on niobium (Nb)thin films, and Josephson junctions comprising a nanometer-thickaluminum oxide insulating layer between two Nb layers. These circuitsfunction at temperatures below 9 K, and preferably below about 4 K.Large-scale integrated circuits have been fabricated with up to 10,000Josephson junctions on a single chip, and up to 10 superconductingwiring layers. See, for example, the following US patents, incorporatedin their entirety by reference:

Double masking technique for increasing fabrication yield insuperconducting electronics (Tolpygo, U.S. Pat. Nos. 9,595,656;9,136,457; 8,383,426; 7,615,385).

System and Method for Providing Multi-conductive Layer Interconnects forSuperconducting Integrated Circuits (Tolpygo, U.S. Pat. Nos. 9,741,920;9,130,116; 8,301,214).

Method for increasing the integration level of superconductingelectronic circuits, and a resulting circuit (Yohannes, U.S. Pat. No.9,741,918).

Systems and Methods for Fabrication of Superconducting IntegratedCircuits (Ladizinsky, U.S. Pat. Nos. 8,951,808; 9,490,296; 9,978,809).

One developing application of superconducting integrated circuits is forclassical computing and memory arrays based on rapid-single-flux-quantum(RSFQ) logic and related technologies, as disclosed in the following USPatents, incorporated in their entirety by reference:

System and Method for Cryogenic Hybrid Technology Computing and Memory(Mukhanov, U.S. Pat. Nos. 9,887,000; 9,520,180).

Superconducting Devices with Ferromagnetic Barrier Junctions (Mukhanov,U.S. Pat. Nos. 9,627,045; 8,971,977).

Low Power Biasing Network for Superconducting Integrated Circuits(Mukhanov, U.S. Pat. Nos. 9,853,645; 9,473,124; 9,240,773; 8,571,614).

Magnetic RAM Array Architecture (Ohki, U.S. Pat. Nos. 9,552,862;9,747,968).

Josephson magnetic random access memory system and method (Herr, U.S.Pat. No. 8,270,209).

See, U.S. Pat. and Pub. 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Another developing application of these circuits is for sensor arraysbased on SQUIDs and similar devices, such as disclosed in the followingUS Patents, incorporated in their entirety by reference:

High Linearity Superconducting Magnetic Field Detector (Kornev, U.S.Pat. Nos. 8,933,695; 8,179,133).

2D Arrays of Diamond Shaped Cells Having Multiple Josephson Junctions(Berggren, U.S. Pat. No. 9,664,751).

Linear voltage response of non-uniform arrays of Bi-SQUIDs (Longhini,U.S. Pat. No. 9,097,751).

Magnetic Resonance System and Method Employing a Digital SQUID(Radparvar, U.S. Pat. Nos. 9,618,591; 9,261,573; 8,618,799; 8,593,141).

Yet another application of superconducting integrated circuits that hasbeen developing more recently is quantum computing using quantum bits(or qubits) made of Josephson junctions, as disclosed in the followingpatents:

System and Method for Controlling Superconducting Quantum Circuits UsingSingle Flux Quantum Logic Circuits (McDermott, U.S. Pat. No. 9,425,804).

System and Method for Circuit Quantum Electrodynamics Measurement(McDermott, U.S. Pat. No. 9,692,423).

Method and apparatus for controlling qubits with single flux quantumlogic (Przybysz, U.S. Pat. No. 7,969,178).

Universal Adiabatic Quantum Computing with Superconducting Qubits(Harris, U.S. Pub. Patent Application No. 2015/0111754).

Superconducting quantum bit device based on Josephson junctions (Esteve,U.S. Pat. No. 6,838,694).

Superconducting shielding for use with an integrated circuit for quantumcomputing (Bunyk, U.S. Pat. No. 7,687,938).

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All of these superconducting systems, both classical and quantum,require careful packaging, particularly as the scale of the systemincreases, and cannot generally be disposed on, or confined to, a singleintegrated circuit device (“chip”). Furthermore, one might havedifferent cryogenic chips optimized for different system applications,such as a quantum computing chip and a digital control chip, which mustbe closely interfaced during operation. These include flip-chipconfigurations and multi-chip modules.

There are several special requirements for bonding superconductingcircuits. First, the voltage levels in superconducting circuits are verylow, so that all contact resistances must be extremely low. Indeed, forsome applications such as quantum computing, the contacts must be fullysuperconducting at the operating temperature. Second, a Josephsonjunction generally comprises an ultrathin tunnel barrier approximately 1nm thick, which is very sensitive to diffusion at elevated temperatures,e.g., of impurities or volatile components in adjacent layers. Indeed,the superconducting critical current I_(c) at the operating temperatureof a Josephson junction may be permanently shifted if the processingtemperature is raised above about 150° C. for an extended period oftime. This has long been known by some in the prior art, but perhaps notwidely appreciated, or avoided during fabrication or processing. Andthird, superconducting circuits are fabricated close to roomtemperature, but operate at deep cryogenic temperatures around 4 K orbelow, and all contacts and packaging must withstand thermal cycling,ideally for multiple thermal cycles between 300 K and 4 K, withoutdegradation of contacts mechanically or electrically. Thus, brittlematerials with mismatched coefficients of thermal expansion should beavoided.

Several distinct approaches to boding superconducting circuit moduleshave been developed, with varying degrees of reliability, scalability,and optimization to superconducting circuits. See the following USPatents, incorporated in their entirety by reference:

Superconductive Multi-Chip Module for High Speed Digital Circuits(Dotsenko, U.S. Pat. No. 9,647,194).

Method for Fabrication of Electrical Contacts to SuperconductingCircuits (Dotsenko, U.S. Pat. No. 8,159,825).

Method of Forming an Electronic Multichip Module (Dotsenko, U.S. Pat.No. 8,804,358).

Systems and Methods for Testing and Packaging a Superconducting Chip(Bunyk, U.S. Pat. No. 9,865,648).

Interconnect structures for assembly of semiconductor structuresincluding superconducting integrated circuits (Oliver, U.S. Pub. PatentApplication No. 2018/0012932).

Cryogenic electronic packages and methods for fabricating cryogenicelectronic packages, (Das, U.S. Pub. Patent Application No.2018/0102469).

Cryogenic electronic packages and assemblies (Das, U.S. Pub. PatentApplication No. 2018/0102470).

Modular array of vertically integrated superconducting qubit devices forscaling quantum computing (Chow, U.S. Pat. No. 9,524,470).

There are also several recent articles in the non-patent literature thatbear upon packaging of superconducting circuits. Note in particular thefollowing:

Foxen, et al, “Qubit compatible superconducting interconnects”, QuantumScience and Technology, vol. 3, no. 1, November 2017, available onlineat iopscience.iop.org/article/10.1088/2058-9565/aa94fc/meta, whichdiscloses the use of pressed indium (In) bumps to form a cold weld atroom temperature without heating. The indium bumps are partiallycompressed, without the use of any posts. It also discloses using adiffusion barrier layer of titanium nitride (TiN) between indium andsuperconducting aluminum.

McRae et al, “Thermocompression bonding technology for multilayersuperconducting quantum circuits”, Applied Physics Letters, vol. 111,123501, September 2017. Available online atarxiv.org/pdf/1705.02435.pdf, which also discloses indium bump bonds,but here the bonds are heated to 190° C., above the melting temperatureof the indium, for 100 minutes.

Reviewing the key aspects of this prior art in packaging ofsuperconducting circuits, Dotsenko (U.S. Pat. Nos. 9,647,194; 8,159,825;8,804,358) uses epoxy bonding, but contacts do not exhibit zeroresistance, and repeated thermal cycling may degrade the quality of thecontacts.

Bunyk (U.S. Pat. No. 9,865,648) discloses using metallic pillars andsolder bumps, but does not address the issue of avoiding hightemperatures in processing, and teaches the use of solder reflow basedon lead-tin (Pb/Sn) solder, which would require temperatures of at least190° C. Such a temperature should be avoided, to avoid changing theproperties of the Josephson junctions.

Oliver (U.S. Pub. Patent Application No. 2018/0012932) and Das (U.S.Pub. Patent Application Nos. 2018/0102469; 2018/0102469) also teach theuse of solder bumps with an underbump metal, using solder reflow. Whilea variety of solder compositions are disclosed, no specific processingtemperatures are given, and there is no teaching of avoidance of hightemperatures due to the sensitivity of Josephson junctions.

Chow (U.S. Pat. No. 9,524,470) discloses superconducting quantumcomputing components using spring-loading and clamps, as well as wirebonds, which do not correspond to a robust scalable technology.

There have also been earlier patents on indium bump bonding, not focusedon superconducting circuits. See, for example, the following U.S.Patents, incorporated in their entirety by reference:

Reworkable Microelectronic Multichip Module (Yokoyama, U.S. Pat. No.5,920,464). Yokoyama discloses cold-welding indium alloys of differentcompositions, in such a way that the weld breaks in a predictablemanner, enabling rework.

Alloy Bonded Indium Bumps and Methods of Processing Same (Williams U.S.Pat. No. 4,930,001). Williams discloses cold welding at room temperatureor up to 100° C., using indium bumps against gold layers. Interdiffusionof indium and gold creates the bond.

Indium alloy cold weld bumps (Helber, U.S. Pat. No. 5,186,379). Helberdiscloses welding an indium bump with an alloying material at anelevated temperature of about 150° C., just below the meltingtemperature of indium (157° C.), but above that of a mixed alloy, sothat the two materials interdiffuse.

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What is needed is a method to bond superconducting integrated circuitsthat is mechanically and electrically reliable, avoids damage tosuperconducting devices, and is scalable to large arrays of smallcontacts. Furthermore, a method that maintains fully superconductingcontacts between superconducting circuits may be essential for quantumcomputing systems. A method with all of these characteristics does notseem to be present in the prior art.

SUMMARY OF THE INVENTION

The invention provides a method for manufacturing an array ofsuperconducting bonds between superconducting circuits on differentchips, such that the operating system of the superconducting circuitscan comprise a plurality of chips in an extended three-dimensionalpackage or multi-chip module (MCM).

In a preferred embodiment, the superconducting circuits comprise niobiumJosephson junctions, and the superconducting bonds comprise indium. Thesuperconducting critical temperature T_(c) of Nb is 9.2° K, and that ofIn is 3.4° K, so that for combined superconducting operation, the MCMmust be cooled below 3.4° K.

In a further preferred embodiment, each chip is manufactured with anarray of copper posts covered with indium bumps, and the chips arepressed together in such a way that the compression of the indium bumpsis stopped by the copper posts, corresponding to a chip separation oforder 4 microns (μm) (see FIGS. 10-12).

In a still further preferred embodiment, a diffusion stopping layer(DSL) is present to prevent interaction of the indium with the copper orthe niobium. This diffusion stopping layer is preferentially alsosuperconducting, so that the conducting path between the chipsNb/DSL/In/DSL/Nb is fully superconducting.

Indium is well known for its unusual mechanical properties; in its pureform, it is a metal with a low melting point, only 157° C., which issomewhat soft and deformable at room temperature, and becomesincreasingly softer as the temperature is increased toward the meltingpoint. It is also a highly reactive metal at moderate temperatures,which tends to form alloys with even lower melting points, but thesealloys tend to be brittle and less deformable.

The use of indium or indium alloys as low-temperature solders is wellknown in the prior art. However, the present invention teaches thatprocessing temperatures should be kept less than 150° C., and preferablyless than 130° C., to avoid altering the properties of the tunnelbarrier that defines the critical current of the Nb Josephson junctions.As such, the indium (or indium alloy) preferably should not reach itsmelting temperature or liquification point.

In a preferred embodiment, compression is carried out at a temperatureof about 75-125° C., whereby the indium is sufficiently soft thatpressures of less than several thousand bars (1 bar=14.7 psi=100 kPa)can compress the package in a controlled and reliable manner in a timethat is less than one hour, even for an assembly with thousands of bumpbonds.

The use of the term “indium” in the present application does notnecessarily require 100% purity, but rather that the electrical,thermal, and mechanical properties are substantially the same as thoseof pure indium. For example, addition of up to 1% of tin into indiumgoes in substitutionally on the atomic level, and remains soft with asimilar melting point, resistivity, and superconducting criticaltemperature. In contrast, significant oxidation of indium leads to amaterial that is hard with poor electrical conduction.

A module made in this way is robust and stable, and can withstandthermal cycling and mechanical mounting multiple times between roomtemperature and an operating temperature of about 3 K. Thesuperconducting critical current of a single indium bond of order 10-30μm in diameter is typically about 10 mA or larger, sufficient todistribute bias currents among Josephson junction circuits. Further, anindium bond can also function to transport signals associated withsingle-flux-quantum (SFQ) voltage pulses, typically 1 mV high by 2 pswide. In addition to small (zero) resistance, this also requires thatthe indium bonds do not have a large inductance (greater than a few pH,consistent with the short interchip spacing), so that these pulses arenot substantially dispersed.

Bonding of chips with several thousand indium bonds has been fabricatedand tested, showing that this process is scalable to higher levels ofintegration. This may be particularly valuable for application to asystem for quantum computing, as shown conceptually in FIG. 16. One chipcould comprise an array of superconducting quantum bits (qubits), whilethe bonded chip could comprise a matched array of SFQ-based control andreadout circuitry. This represents an embodiment of a quantum-classicalMCM assembly, comprising, for example, at least one quantum chip and atleast one classical chip.

FIGS. 17A-17D show several preferred embodiments of configurations forbonding a quantum circuit (comprising qubits) to a classical circuit(comprising, e.g., SFQ circuits). The circuits from the two chips may bein close contact, or alternatively they may be located on opposite sidesof their respective chips. In the latter case, through-chip vias (whichmay comprise superconducting connections) may provide coupling to theelectrical contacts between the chips. Furthermore, high-frequencysignal connections between the two chips may be enabled with inductiveor capacitive coupling, rather than just direct electrical (galvanic)coupling.

There may be a further advantage for the use of copper posts in thecontext of quantum circuits. It is known in the literature that when asuperconductor (such as niobium or indium) is in good electrical contactwith a normal metal such as copper, hot electrons (also known as excitedquasiparticles) may be trapped in the normal metal. This is particularlytrue at very low temperatures, when the superconducting energy gap ismuch greater than thermal energy k_(B)T. Such excited quasiparticles maybe generated by classical SFQ circuits, which include electricalresistors. It is also known in the literature that such excitedquasiparticles may act to reduce the coherence time of qubits, thuslimiting their functionality. The presence of copper posts in theelectrical contacts between classical and quantum circuits may act totrap excited quasiparticles, thus reducing the leakage of suchquasiparticles from the classical to the quantum circuits. This may tendto improve the performance of the quantum circuits, as compared toquantum circuits with bonds that do not include copper posts.

While the intention of preferred embodiments is generally to bond chipstogether permanently, in an alternative embodiment, the process may bealtered slightly so that the two chips may be detached after preliminarytesting, without significant damage to either chip. Such an alternativeprocess may comprise slightly reduced temperature, pressure, and/orprocessing time. Furthermore, detachment (debonding) may be assisted byrelatively gentle mechanical means such as a localized burst ofhigh-pressure air, which would also not cause significant damage to thechips.

Further embodiments of the system and method for bonding superconductingchips are presented later in the Detailed Description section, togetherwith a more complete explanation of the figures. These examplesrepresent preferred embodiments of the invention, but the invention isnot restricted to these examples, and other embodiments and applicationsthat follow the same principles are also covered.

It is therefore an object to provide a method for interconnectingelectronic circuits, comprising: depositing a plurality of metallicposts on each electronic circuit; depositing a respective indium bump oneach respective metallic post; aligning the indium bumps of therespective electronic circuits; and applying heat at a temperature belowa melting temperature of the indium, and sufficient pressure between therespective electronic circuits, to deform and cold-weld the plurality ofaligned indium bumps on the respective electronic circuits, to form abonded circuit having a plurality of cold-welded indium bonds.

The indium between the aligned metallic posts is plastically deformedand at least a portion is displaced from the space between the tips ofthe metallic posts. The indium forms a continuous sleeve around themetallic posts between the two electronic circuits. The heat softens theindium, to reduce its resistance to plastic deformation. The amount ofcompression is limited to avoid cracking of the indium film or unduepressure on the electronic circuits. The compression may continue untilthe aligned metallic posts contact, and the tips of the metallic postsmay be shaped to facilitate such contact. The impedance betweenrespective metallic posts may be measured to determine their contactstatus.

The heat may be applied at a temperature of between 50° C. and 150° C.

The sufficient pressure may be applied by a fixture configured tomaintain the alignment of the indium bumps during application of thesufficient pressure. The fixture may be a flip chip bonder. The methodmay further comprise removing the bonded circuit from the fixture. Thebonded circuit may be cooled to a temperature at which the indium issuperconductive.

At least one electronic circuit may comprise a Josephson junction, themethod further comprising cooling the at least one electronic circuit,and producing at least one pulse with the Josephson junction.

A diffusion barrier may be deposited under each respective indium bump.The diffusion barrier may comprise a superconducting compound, e.g.,niobium nitride or titanium nitride.

The electronic circuits may be fabricated on a wafer, with at least oneelectronic circuit located on the opposite side of the wafer from theindium bumps. A through-wafer via may be provided which enableselectrical connection from the electronic circuit to the indium bumps onthe opposite side of the wafer.

The metallic post may comprise copper. Alternates are gold alloy (forhardness), silver, niobium, or other metals. In general, the metallicpost should have substantially lower deformation under the compression,so that it remains dimensionally stable.

One of the electronic circuits may comprise a carrier for a multi-chipmodule. A plurality of electronic circuits may be bonded to the samecarrier.

At least one of the electronic circuits may comprise niobium, aluminum,niobium-titanium, or niobium nitride.

At least one of the indium bonds may be electrically connected to aground layer. The ground layer may be a superconducting ground layer.

At least one indium bump may be about 30 micrometers or less indiameter. For example, it may be 30, 25, 20, 15, 10, or 5μm in diameter.

The method may further comprise cooling the bonded circuit to a deepcryogenic temperature less than or equal to 3.4° K, e.g., 3.4° K, 3.3°K, 3.2° K, 3.1° K, 3.0° K, 2.75° K, 2.5° K, 2.25° K, 2.0° K, 1.0° K,0.5° K, 0.25° K, 0.1° K, etc.

The bonded circuit may comprise a superconducting electronic device, andthe cold-welded indium bonds may be configured to carry an electricalcurrent without resistance of at least about 10 mA.

At least one of the electronic circuits may comprise at least one qubit.At least one of the electronic circuits may comprise asingle-flux-quantum logic circuit. At least one of the electroniccircuits may comprise at least one superconducting electromagneticsensor.

The heating at the temperature below the melting temperature of theindium may comprise heating the aligned bumps to a temperature less thanabout 150° C., e.g., 150° C., 140° C., 130° C., 120° C., 110° C., 100°C., 90° C., 80° C., 70° C., or 60° C.

The applying a sufficient pressure may comprise applying a uniaxialpressure less than five thousand bars applied across the plurality ofbumps for a period of less than one hour. For example, the pressure maybe 5000 bars, 4000 bars, 3000 bars, 2500 bars, 2000 bars, 1500 bars,1200 bars, 1000 bars, or lower. The time of compression may be 100minutes, 75 minutes, 60 minutes, 45 minutes, 30 minutes, 20 minutes, 15minutes, 10 minutes, 8 minutes, 5 minutes, 4 minutes, 3 minutes, 2minutes, or 1 minute.

The alignment of the indium bumps may be achieved using alignment marksin a flip-chip bonder.

The plurality of metallic posts may serve to maintain a uniformseparation between the two electronic circuits after compression.

A respective pair of aligned metallic posts may be compressed todisplace the indium on top of each respective metallic post.

The number of functional cold-welded indium bonds on at least oneelectronic circuit may exceed 1000.

The electrical properties of the cold-welded indium bonds may permit thetransmission between the electronic circuits of fast pulse trains ofpicosecond single-flux-quantum voltage pulses below a superconductingtemperature of the indium.

The bonded circuits are adapted to be fully debonded without damagingthe electronic circuits.

Another object provides a multi-chip module comprising at least twosuperconducting electronic chips bonded to a superconducting carrier viaa plurality of indium bumps, each indium bump comprising an indiumcoating on a metallic post, wherein opposing indium bumps are compressedand heated below a melting temperature of the indium to form acold-welded bond that functions as a superconducting interconnectbetween superconducting circuits on the respective electronic chips andcarrier, when cooled to deep cryogenic temperatures. A diffusion barrierlayer may be provided between the indium and the metallic post. Thecold-welded bond permits the transmission of picosecondsingle-flux-quantum voltage pulses between the superconducting carrierand a superconducting chip bonded to the carrier.

In order to assist in maintaining the integrity of the cold-weldedbonds, a cryogenically stable adhesive, such as an epoxy may be providedin a gap between the electronic circuits.

The module may comprise at least one quantum circuit and at least oneclassical circuit, wherein the at least one classical circuit functions,e.g., to control the quantum circuit and read out signals from thequantum circuit.

Other objects will become apparent through a review of the descriptionprovided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-7 illustrate a preferred embodiment of the steps to fabricate anarray of indium bumps on a superconducting circuit.

FIG. 1 shows the deposition of a superconducting ground plane.

FIG. 2 shows the deposition of an insulating layer above the groundplane shown in FIG. 1, with holes through to the ground plane.

FIG. 3 shows the deposition of a superconducting wiring layer on theinsulating layer of FIG. 2, forming vias to the ground plane, and alarge contact pad.

FIG. 4 shows the deposition of a gold contact pad connecting to thesuperconducting wiring layer of FIG. 3.

FIG. 5 shows the deposition of copper posts on top of thesuperconducting vias of FIG. 4.

FIG. 6 shows the deposition of a diffusion stopping layer on top of thecopper posts of FIG. 5.

FIG. 7 shows the deposition of indium bumps on top of the diffusionstopping layer of FIG. 6.

FIG. 8 shows the cross section of two bump bonds before bonding.

FIG. 9 shows a photograph of a carrier chip and a matching flip chip,each with an array of 2066 bumps.

FIG. 10 shows the flip-chip alignment configuration for bonding to thecarrier chip.

FIG. 11 shows a cross-sectional view of two aligned bonds before fullcompression.

FIG. 12 shows a cross-sectional view of two aligned bonds after fullcompression.

FIG. 13 shows a measurement of the resistance of a series of bonds as afunction of cryogenic temperature.

FIG. 14 shows a measurement of V(I) for a series of superconductingindium bonds, showing a large critical current.

FIG. 15 shows a measurement of the superconducting critical current of aseries of bonds as a function of cryogenic temperature.

FIG. 16 shows a conceptual picture of a set of two bonded chips for aquantum computing application.

FIGS. 17A-17D show four alternative configurations for bonding a quantumcircuit to a classical circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 through 7 show steps of a preferred embodiment of the method forpreparing indium bump bonds on superconducting Nb chips, integrated intoa prior-art method for fabricating superconducting integrated circuits.All of these are designed to be carried out on an entire 150 mm siliconwafer, although only a 2-mm portion of a single chip is shown forsimplicity.

FIG. 1 shows Step 1, the deposition of a superconducting Nb ground planecomprising 100 nm of sputtered Nb on top of an oxidized silicon wafer,known in the Hypres standard process(www.hypres.com/foundry/niobium-process/;www.hypres.com/wp-content/uploads/2010/11/DesignRules-6.pdf; Yohannes,D., et al., “Parametric Testing of HYPRES Superconducting IntegratedCircuit Fabrication Processes”, IEEE Trans. Applied Superconductivity,V. 17, No. 2, June 2007, pp. 181-186,www.hypres.com/wp-content/uploads/2010/12/Parameter-Testing.pdf) as thelayer M0. The small circles show the ultimate locations of the indiumbumps, which are not yet present.

FIG. 2 shows Step 2, the deposition of 150 nm of insulating silicondioxide (SiO₂, typically deposited using plasma-enhanced chemical vapordeposition, or PECVD) on top of the Nb, with an array of patterned holesto establish electrical conducting vias to the next conducting layer.The holes have diameters of about 30 μm or less.

FIG. 3 shows Step 3, the deposition of 300 nm of superconducting Nb thatcan represent a superconducting signal or a via to ground. Also shown isa large pad on the right that connects to this layer.

FIG. 4 shows Step 4, the deposition of a large contact pad for externalconnections, comprising 100 nm Ti and 100 nm Pd followed by 200 nm Au.This establishes a well-adhering pad for external contacts fromgold-plated pins.

Steps 1 through 4 comprise steps similar to the fabrication of aprior-art superconducting integrated circuit. Not shown are otherstandard steps of the prior-art methods, including depositing anddefining Josephson junctions of Nb/Al/AlOx/Nb, using controlledoxidation and anodization, depositing a resistive layer such as Mo,additional wiring layers, and steps of planarization. Also, in each casewhenever a conducting film is deposited on a sample that has beenpatterned outside the vacuum system, an initial cleaning step in anargon plasma may be used to ensure unoxidized interfaces.

FIG. 5 shows Step 5, the evaporation deposition of an array of 2 μmthick Cu posts on top of the small Nb contacts. Note that the Cu posthas a slightly smaller diameter than the Nb contact, leaving a Nb ringaround it. These Cu posts can be on ground contacts or signal contacts.The use of Cu is not unique; another metal that is not deformable (orless deformable that the indium under the compression conditions) wouldalso be acceptable, such as Nb, Mo, Ti, Au, etc.

FIG. 6 show Step 6, the deposition of 100 nm of a diffusion stoppinglayer (DSL) on top of the Cu posts and the Nb ring around each post.Preferred DSL materials include NbN and TiN, both of which can beprepared by reactive sputtering in a gas that includes nitrogen.

FIG. 7 shows Step 7, the evaporation deposition of 2 μm of indium on topof the DSL. Pure indium is preferred, since indium alloys tend to have amulti-phase microstructure that is harder and more brittle. Themetallized patterns may be etched after deposition to form the isolatedregions on top of other features.

FIG. 8 shows the cross section of two of the bumps prepared according toSteps 5 through 7 above, before the chips are pressed together, showingthe indium bump, diffusion stopping layer, and copper post on top of theNb contact. The numbers on the left indicate the approximate layerthicknesses in nm for a preferred embodiment.

FIG. 9 shows a photograph of a 10 mm carrier chip and a 5 mm flip chip,each with 2066 bumps, matching on both chips. These bumps comprise 1000signal bumps (25 rows of 40 bumps each, 30 μm in diameter with 80 μmpitch) alternating with 1066 ground bumps. The carrier chip hasgold-plated ground and signal contacts around its periphery, forexternal biasing and signal measurement. All 1000 signal bumps could bemeasured at the same time, or any of the 25 rows could be measuredindependently. Two other similar test structures were also tested usingcarrier and flip chips of the same size: The first structure had 300signal bumps (15 rows of 20 bumps each, 30 μm in diameter with 130 μmpitch) alternating with 366 ground bumps, where all signal bumps couldbe measured together, or with independent rows. The second structure had2691 signal bumps (39 rows of 69 bumps each, 15 μm in diameter with 50μm pitch) alternating with 3353 ground bumps.

After removal of the wafer from the deposition system, the individualchips are separated (diced) using a commercial dicing machine. If therewill be a significant delay before flip-chip bonding, the chips shouldbe maintained in an environment that minimizes oxidation of the indiumsurfaces. The presence of significant oxide layers on indium surfacesmay reduce the reliability of the method. For example, the chips may beimmersed in a bath of methanol. Alternatively, just before bonding, theindium bumps may be subjected to an argon plasma etch to remove anaccumulated surface oxide.

FIG. 10 shows how the bumps on the flip chip are aligned with thecorresponding bumps on the carrier chip, with the help of the smallalignment marks noted. This may be carried out using a commercialflip-chip bonder, such as the Karl Suss MicroTec FC-150, which permitsmicron alignment resolution. This bonder also allows controlledcompression and temperature. For each structure, the chips were heatedto about 75-125° C., using a force up to 20 kg (i.e., 200 Nt or 44 lb)for a period of about 15 minutes. Given the contact area of the bonds,this force corresponded to a uniaxial pressure up to several thousandbars.

FIG. 11 provides a cross-sectional view of aligned indium bumps ascompression is initiated, with a thick layer of In between the twoDSL/copper posts. Thicknesses of layers are not drawn to scale.

FIG. 12 provides a cross-section of aligned bumps as compression iscompleted, with most of the indium between the two DSL/copper postssqueezed out. Since the DSL/Cu is not compressed, this provides a hardstop for the separation of the two chips, about 4μm for the stepspresented. While current can flow through the Cu posts in the resistivestate, the superconducting indium shorts out the C.u below 3.4° K,providing a fully superconducting current path. Thicknesses of layersare not drawn to scale.

FIG. 13 shows the resistance of a series of In bonds as a function oftemperature. The resistance drops sharply when the Nb goessuperconducting at 9° K, and drops to zero when the In goessuperconducting at 3.4° K.

FIG. 14 shows the current-voltage curve V(I) for a series of In bonds at3° K, showing a sharp rise in voltage at the critical current of 15 mA.The large local power dissipation then heats up the In above itscritical temperature 3.4° K, until the current is lowered down to 3 mA,when the voltage drops to zero. This sort of hysteresis related to localheating is characteristic of current-driven transitions insuperconducting wires.

FIG. 15 shows the critical current of In bonds as a function oftemperature below 3.4° K, showing a typical dependence rising as thetemperature is cooled further. Any operating temperature at about 3° K.or below would be compatible with fully superconducting interconnects.

These tests were carried out for chips mounted on a cryocooler, acryogenic refrigerator that uses helium as a working fluid, designed tocool down to temperatures as low as 3° K. Even lower temperatures can beachieved if the working fluid comprises the isotope helium-3, especiallyif the refrigerator is configured as a helium dilution refrigerator,which can achieve temperatures less than 0.1° K.

The tests based on the chips fabricated according to the disclosedoptimized processes and parameters demonstrated very high yields onmultiple chips, each with thousands of bonds. Further, the results wereduplicated with multiple thermal cycles between room temperature and 3°K, indicating robust and reproducible contacts.

FIG. 16 provides a conceptual picture of a two-chip package, where onechip comprises superconducting quantum bits (qubits), and the othercomprises single-flux-quantum control and readout circuits. Each ofthese chips might be manufactured with a distinct process, as long asboth may be combined with indium bump bonds and copper posts. Forexample, the qubit chip might be prepared using aluminum Josephsonjunctions and NbTi wiring for transmon qubits, while the control chipmight be prepared with Nb Josephson junctions and Nb wiring forenergy-efficient SFQ circuits. The entire package could operate at verylow temperatures (much less than 1° K) typical of superconductingquantum computing. Further, a three-dimensional quantum computingpackage need not be limited to two chips. One could also have amulti-chip module comprising a plurality of flip chips on a singlecarrier.

A further set of preferred embodiments for quantum-classical MCMs isillustrated in FIGS. 17A-17D. The simplest of the configurations isshown in FIG. 17A, where the quantum circuits at the bottom of thequantum chip are in close proximity to the classical circuits of theclassical chip. There may be a concern that classical SFQ circuits maygenerate some hot electrons (excited quasiparticles), which may migrateto the quantum circuits and degrade their performance. However, asmentioned above, the presence of the copper posts in the bonds betweenthe classical and quantum circuits may tend to trap at least asignificant fraction of the excited quasiparticles, keeping them fromcontaminating the quantum circuits.

Furthermore, the classical and quantum circuits may be further separatedby placing them on opposite sides of the chips, as shown in FIGS. 17B,17C, and 17D. This would likely reduce further any remaining deleteriouseffects of the excited quasiparticles. These latter structures may besomewhat more complex to manufacture, requiring etching through-wafervias, but similar vias are well known in silicon chip manufacturing.These through-wafer vias can be coated with a superconducting film, suchas Nb, Al, or In, enabling a superconducting bias current or electricalsignal to be transmitted from one side of the chip to the other, withoutloss or dissipation. Depending on the desired configuration, the throughvias may be present in either the classical chip, or the quantum chip,or both. In some cases, it may be desirable to include circuits on bothsides of one or more chips.

An alternative application of this packaging technology might be forclassical supercomputers, with large numbers of superconductingmicroprocessors operating in parallel at frequencies of 50-100 GHz. Thiswould also require close integration with cryogenic fast cache memorychips in the same cryogenic environment. One can envision, for example,a set of multi-chip modules, each comprising both cryogenic processorsand memory, as well as cryogenic input-output chips that communicate toslower processors and memory at higher temperatures.

A further alternative application of this packaging technology might befor superconducting sensor arrays, which have been demonstrated formagnetic field detection, imaging arrays for astronomy and high-energyphysics, and biomedical imaging. Such sensor arrays may further beintegrated with superconducting digitizers, digital signal processors,and digital controllers, preferably in the same cryogenic environment asthe sensors. This would require a set of multi-chip modules combiningsensor chips with digital processing chips.

While superconducting multichip modules and indium bonding have beendisclosed in the prior art, the present technology presents asubstantial improvement. Much of the prior art focuses on solder reflowat moderately high temperatures, which would alter the preciseparameters of the sensitive Josephson junctions on the chips. Otherprior art uses unheated cold-welding of indium, which we have found isimpractical for scaling to large numbers of bonds, because that wouldrequire pressures that are so large as to risk damaging or cracking thechips or substrates. We have found that a good compromise is anintermediate processing temperature about 75-125° C., but preferablyless than 150° C., where the indium is somewhat softer, and neither thetemperature nor the pressure risks damage to the chips.

Another aspect of the prior art of indium bonding is that diffusion andalloying was favored, because the alloy is harder and achieves a morerigid bond. On the contrary, the present invention attempts to reduce oreliminate diffusion and alloying using a diffusion stopping layer (DSL)between the indium and all other metals. This suppresses the formationof brittle intermetallics that would limit plastic flow of the In aroundthe Cu post. Also, the preferred DSL is also superconducting (such asNbN and TiN), so that it may form a sharp superconducting interfacebetween the In and the Nb.

Other devices, apparatus, systems, methods, features and advantages ofthe invention will be or will become apparent to one with skill in theart upon examination of the following figures and detailed description.It is intended that all such additional systems, methods, features andadvantages be included within this description, be within the scope ofthe invention, and be protected by the accompanying claims.

What is claimed is:
 1. An interconnect for connecting electroniccircuits, comprising a plurality of cold-welded indium bonds, eachindium bond comprising a pair of aligned opposing posts, each havingpost having an indium bump which is cold-welded at a temperature notgreater than a melting temperature of the indium bump, and under asufficient pressure to deform and cold-weld the indium bumps of the pairof aligned opposing posts.
 2. The interconnect according to claim 1,wherein the temperature not greater than a melting temperature of theindium bump is a temperature of between 50° C. and 150° C.
 3. Theinterconnect according to claim 1, wherein at least one electroniccircuit comprises a cryogenic Josephson junction.
 4. The interconnect ofclaim 1, further comprising a diffusion barrier under each respectiveindium bump.
 5. The interconnect of claim 4, wherein the diffusionbarrier comprises a superconducting compound selected from the groupconsisting of niobium nitride and titanium nitride.
 6. The interconnectof claim 1, wherein the indium bumps are formed on a rear of anintegrated circuit wafer with respect to electronic circuits fabricatedon the wafer, and through-wafer vias enable electrical connection fromthe electronic circuit to the indium bumps on the opposite side of thewafer.
 7. The interconnect of claim 1, wherein at least one opposingpost comprises a copper post.
 8. The interconnect of claim 1, whereinthe electronic circuits comprise a plurality of electronic circuitsbonded to a common carrier for a multi-chip module.
 9. The method ofclaim 1, wherein at least one of the cold-welded indium bondselectrically connects to a superconducting ground layer.
 10. The methodof claim 1, wherein at least one indium bump is about 30 micrometers orless in diameter.
 11. The method of claim 1, wherein at least one of theelectronic circuits comprises a superconducting electronic device, andthe cold-welded indium bonds are configured to carry an electricalcurrent of at least about 10 mA without resistance at a temperature ofless than 3.4° K.
 12. The method of claim 1, wherein at least one of theelectronic circuits comprises at least one qubit.
 13. The method ofclaim 1, wherein at least one of the electronic circuits comprises asingle-flux-quantum logic circuit.
 14. The method of claim 1, wherein atleast one of the electronic circuits comprises a superconductingelectromagnetic sensor.
 15. The method of claim 1, wherein thesufficient pressure comprises a uniaxial pressure of less than fivethousand bars applied across the plurality of bumps for a period of lessthan one hour.
 16. An electronic circuit module, comprising at least twoelectronic circuit substrates, each substrate having a plurality ofposts, wherein the plurality of posts of the at least two electroniccircuit substrates are aligned and bonded by a respective cold-weldedindium bond between a respective pair of posts.
 17. The electroniccircuit module according to claim 16, wherein at least one electroniccircuit substrate comprises a cryogenic Josephson junction.
 18. Theelectronic circuit module according to claim 17, further comprising asuperconducting diffusion barrier between the cold-welded indium bondand a supporting metal post.
 19. The electronic circuit module accordingto claim 16, wherein the posts are disposed on a surface of anintegrated circuit wafer opposite a fabricated electronic circuit on theintegrated circuit wafer, with through-wafer vias connecting thefabricated integrated circuit to the cold-welded indium bond.
 20. Amulti-chip module comprising at least two superconducting electronicchips interconnected through a plurality of indium bumps, each indiumbump comprising an indium coating on a post, wherein opposing indiumbumps are compressed and heated below a melting temperature of theindium to form a cold-welded bond.